Valery Solovjev, Irena Bulatova: Synthesis of One-Stage Digital Circuits Based on Generic Array Logics CSIT 2000 : 286-290
In the paper a method of logic synthesis of one-stage digital circuits on the base of Generic Array Logic (GAL) is proposed. Unlike the traditional approach to the logic synthesis on PLD, this method takes in account special internal resources and architectural features of GAL structures at the earliest stages of project design that allows increase the efficiency of logic synthesis. The conditions of possibility of logical synthesis of one-stage circuits are formulated. The high performance of one-stage circuits (limited only by the performance of the GAL) and weak limitations on the parameters of the set of Boolean functions made this method very useful in practice.
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Heinz Schweppe and Yuri S. Kabalnov (Eds.): CSIT'2000, Proceedings of 2nd International Workshop on Computer Science and Information Technologies, September 18-23, 2000, Ufa, Russia. USATU Publishers & JurInfoR-MSU Publishing 2000, ISBN 5-86911-312-1